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1 LTC3770 3770f , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. no r sense is a trademark of linear technology corporation. protected by u.s. patents including 5481178, 5487554, 6580258, 6304066, 6476589, 6774611. fast no r sense tm step-down synchronous controller with margining, tracking and pll wide v in range: 4v to 32v 0.67% 0.6v reference voltage output voltage tracking capability programmable margining sense resistor optional true current mode control 2% to 90% duty cycle at 200khz t on(min) 100ns phase lock loop frequency synchronization powerful dual n-channel mosfet driver adjustable cycle-by-cycle current limit adjustable switching frequency programmable soft-start current foldback protection (disabled at start-up) output overvoltage protection micropower shutdown: i q < 30 a power good output voltage monitor tracks the reference input pin available in (5mm 5mm) qfn and 28-lead ssop packages distributed power systems server power supply the ltc 3770 is a synchronous step-down switching regulator controller with output voltage up/down tracking capability and voltage margining. its advanced functions and high accuracy reference are ideal for powering high performance server, asic and computer memory systems. the LTC3770 uses a constant on-time, valley current mode control architecture to deliver very low duty factors without requiring a sense resistor. the operating fre- quency is selected by an external resistor and is compen- sated for variations in input supply voltage. an internal phase-lock loop allows the ic to be synchronized to an external clock. fault protection is provided by an overvoltage comparator and input undervoltage lockout. the regulator current limit is user programmable. a wide supply range allows volt- ages as high as 32v to be stepped down to as low as a 0.6v output. power supply sequencing is accomplished using an external soft-start timing capacitor. high efficiency step-down converter descriptio u features applicatio s u typical applicatio u cmdsh-3 b340a 95.3k 30.1k 10k 82k 1.8 h 10 f 10 f 35v x3 v in 5v to 28v v out 2.5v 10a 180 f 4v x2 si4874 si4884 68k 0.1 f 0.22 f 10k 1000pf v out 10k 0.01 f + i on v in tg sw boost pllin run i th sgnd intv cc bg pgnd sense sense + v fb v refin LTC3770 drv cc pgood mpgm v refout v on v rng margin track/ss pllfltr 3770 ta01 load current (a) efficiency (%) 100 90 80 70 60 50 95 85 75 65 55 power loss (w) 10 0.1 1 0.01 0.01 1 10 3770 ta01b 0.1 v in = 5v v out = 2.5v efficiency power loss efficiency and power loss vs load current
2 LTC3770 3770f 32 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 33 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 v rng v fb i th sgnd margin1 margin0 i on v refin sense + sense pgnd bg drv cc intv cc z2 z1 pgood v on run fcb z0 boost tg sw v refout mpgm track/ss pllfltr pllin v in v insns zv in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 run v on pgood v rng v fb i th sgnd margin1 margin0 i on v refin v refout mpgm track/ss fcb z0 boost tg sw pgnd bg intv cc z2 z1 zv in v in pllin pllfltr input supply voltage (v in , v insns ) ............32v to 0.3v boosted topside driver supply voltage (boost) ................................................38v to 0.3v sense + , sw voltage ....................................32v to 5v drv cc , (boost ?sw) voltages .................7v to 0.3v v on , v rng , pgood voltages .... intv cc + 0.3v to 0.3v pllfltr, i th , v fb , v refin voltages .......... 2.7v to 0.3v track/ss, fcb, z0, z1, z2, run, pllin, margin0, margin1 voltages ............... intv cc + 0.3v to 0.3v absolute axi u rati gs w ww u package/order i for atio uu w order part number LTC3770eg g part marking LTC3770eg t jmax = 125 c, ja = 130 c/ w consult ltc marketing for parts specified with wider operating temperature ranges. (note 1) intv cc , zv in voltages .................................7v to 0.3v tg, bg, intv cc peak currents ................................... 4a tg, bg, intv cc rms currents ............................. 50ma operating ambient temperature range (note 4) ................................... 40 c to 85 c junction temperature (note 2) ............................. 125 c storage temperature range ................. 65 c to 125 c qfn reflow peak body temperature .................... 245 c lead temperature (soldering, 10 sec).................. 300 c order part number LTC3770euh uh part marking 3770 t jmax = 125 c, ja = 34 c/ w exposed pad is sgnd (pin 33) must be soldered to the pcb
3 LTC3770 3770f the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 15v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units main control loop i q input dc supply current normal operation 1300 2200 a shutdown supply current 30 50 a v fb feedback voltage accuracy (note 3) v refin = v refout ; i th = 1.2v (0 c to 85 c) 0.596 0.6 0.604 v v refin = v refout ; i th = 1.2v 0.594 0.6 0.606 v v fb(linereg) feedback voltage line regulation v in = 4v to 30v, i th = 1.2v (note 3) 0.002 %/v v fb(loadreg) feedback voltage load regulation i th = 0.5v to 1.9v (note 3) 0.05 0.3 % v run run pin on threshold v run rising 1 1.5 1.9 v i ss/track soft-start charging current v ss/track = 0v ?.1 ?.4 ?.7 a i fb feedback pin input current ?00 20 100 na g m(ea) error amplifier transconductance i th = 1.2v (note 3) 1 1.3 1.6 ms v fcb forced continuous threshold 0.57 0.6 0.63 v i fcb forced continuous pin current v fcb = 0v 1 2 a t on on-time i on = ?0 a, v on = 1.5v 210 250 290 ns i on = ?0 a, v on = 0v 90 115 150 ns t on(min) minimum on-time i on = ?80 a, v on = 0v 50 100 ns t off(min) minimum off-time 250 400 ns v sense(max) maximum current sense threshold v rng = 1v, v fb = v refin ?30mv 113 133 153 mv v sense ?v sense + v rng = 0v, v fb = v refin ?30mv 50 67 84 mv v rng = intv cc , v fb = v refin ?30mv 228 268 308 mv v sense(min) minimum current sense threshold v rng = 1v, v fb = v refin + 30mv 60 mv v sense ?v sense + v rng = 0v, v fb = v refin + 30mv 30 mv v rng = intv cc , v fb = v refin + 30mv 120 mv ? v fb(ov) output overvoltage fault threshold offset 7 10 13 % v in(uvlo + ) undervoltage lockout v in falling 3.2 3.9 v v in(uvlo ) undervoltage lockout v in rising 3.3 4 v v mgn(th) margin0, margin1 input thresholds 1.4 v v mpgm mpgm pin voltage 1.18 v tg r up tg driver pull-up on resistance tg high 1.9 2.5 ? tg r down tg driver pull-down on resistance tg low 1.2 2.5 ? bg r up bg driver pull-up on resistance bg high 1.9 3 ? bg r down bg driver pull-down on resistance bg low 0.7 1.5 ? tg t r tg rise time c load = 3300pf 20 ns tg t f tg fall time c load = 3300pf 20 ns bg t r bg rise time c load = 3300pf 20 ns bg t f bg fall time c load = 3300pf 20 ns
4 LTC3770 3770f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d as follows: LTC3770eg: t j = t a + (p d ?130 c/w) LTC3770euh: t j = t a + (p d ?34 c/w) note 3: the 3770 is tested in a feedback loop that adjusts v fb to achieve a specified error amplifier output voltage (i th ). for these tests, v refout = v refin . note 4: the LTC3770e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the ?0 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 15v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units internal v cc regulator v intvcc internal v cc voltage 6v < v in < 30v 4.7 5 5.3 v ? v ldo(loadreg) internal v cc load regulation i cc = 0ma to 20ma 0.1 2% phased-locked loop r pllin pllin input resistance 50 k ? i pllfltr phase detector output current sink capability f pllin < f 0 ?5 a source capability f pllin > f 0 15 a pgood output ? v fbh pgood upper threshold v fb rising 7 10 13 % ? v fbl pgood lower threshold v fb falling 7 10 13 % ? v fb(hys) pgood hysteresis v fb returning 1.5 3 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v typical perfor a ce characteristics uw on-time vs i on current on-time vs v on voltage current sense threshold vs i th voltage i th voltage (v) 0 200 current sense threshold (mv) 100 0 100 200 300 0.5 1.0 1.5 2.0 3770 g01 2.5 3.0 v rng = 1v 0.7v 0.5v 1.4v 2v i on current ( a) 1 10 on-time (ns) 100 1k 10k 10 100 3770 g02 v von = 0v v on voltage (v) 0 on-time (ns) 400 600 3770 g03 200 0 1 2 5 4 3 1200 1000 800 i ion = 60 a
5 LTC3770 3770f typical perfor a ce characteristics uw maximum current sense threshold vs temperature maximum current sense threshold vs v rng voltage v rng voltage (v) 0.5 0 maximum current sense threshold (mv) 50 100 150 200 300 0.75 1.0 1.25 1.5 3770 g05 1.75 2.0 250 temperature ( c) 50 ?5 100 maximum current sense threshold (mv) 120 150 0 50 75 3770 g06 110 140 130 25 100 125 v rng = 1v temperature ( c) ?0 on-time (ns) 200 250 300 25 75 3770 g04 150 100 ?5 0 50 100 125 50 0 i ion = 30 a v von = 0v on-time vs temperature input voltage (v) 0 input current (ma) 1.5 2.0 2.5 15 25 3770 g08 1.0 0.5 510 20 30 35 0 input current vs input voltage error amplifier g m vs temperature temperature ( c) 50 ?5 0.6 g m (ms) 1.0 1.6 0 50 75 3770 g07 0.8 1.4 1.2 25 100 125 shutdown current vs input voltage input voltage (v) 0 shutdown current ( a) 15 25 3770 g09 510 20 30 35 30 40 60 50 20 10 0 fcb pin current vs temperature undervoltage lockout threshold vs temperature temperature ( c) ?0 fcb pin current ( a) 0.50 0.25 0 25 75 3770 g11 0.75 1.00 ?5 0 50 100 125 1.25 1.50 temperature (c) ?0 2.0 undervoltage lockout threshold (v) 2.5 3.0 3.5 4.0 25 0 25 50 3770 g12 75 100 125 intv cc load current (ma) 0 ? intv cc (%) 0.2 0.1 0 40 3770 g10 0.3 0.4 10 20 30 50 intv cc load regulation
6 LTC3770 3770f typical perfor a ce characteristics uw transient response track down track up i th voltage vs load current efficiency vs load current frequency vs input voltage v out 2v/div track/ss and v fb 500mv/div 250ms/div 3770 g13 track/ss figure 12 circuit v fb v out v out 2v/div track/ss and v fb 500mv/div 250ms/div 3770 g14 track/ss v fb v out figure 12 circuit v out 100mv/div i l 5a/div step 0a to 10a 20 s/div 3770 g15 figure 12 circuit load current (a) efficiency (%) 100 90 95 85 80 75 50 55 60 65 70 0.01 1 10 3770 g16 0.1 discontinuous mode continuous mode figure 12 circuit input voltage (v) frequency (khz) 480 460 440 420 400 300 320 340 360 380 02030 25 3770 g18 10 15 5 fcb = 0v figure 12 circuit i out = 10a i out = 0a load current (a) i th voltage (v) 2.5 1.5 2.0 1.0 0.5 0 0812 10 3770 g17 46 2 discontinuous mode figure 12 circuit continuous mode frequency vs load current efficiency vs input voltage input voltage (v) efficiency (%) 100 95 90 85 80 70 75 02030 25 3770 g19 10 15 5 fcb = 5v figure 12 circuit i load = 10a i load = 1a load current (a) 0812 10 46 2 frequency (khz) 500 450 400 350 300 250 0 50 100 150 200 3770 g20 discontinuous mode continuous mode figure 12 circuit
7 LTC3770 3770f v fb (v) 0 0 maximum current sense threshold (mv) 160 0.1 0.2 0.3 0.4 3770 g21 0.5 0.6 80 60 40 140 120 20 100 v rng = 1v typical perfor a ce characteristics uw uu u pi fu ctio s v rng (pin 1/pin 4): sense voltage range input. the voltage at this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5v to 2v by a resistive divider from intv cc . the nominal sense voltage defaults to 50mv when this pin is tied to ground, 200mv when tied to intv cc . do not set this voltage between 0.5v to ground or 2v to intv cc . v fb (pin 2/pin 5): error amplifier feedback input. this pin connects the error amplifier input to an external resistive divider from v out . i th (pin 3/pin 6): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.75v corresponding to zero sense voltage (zero current). there is an integrated ca- pacitor of 20pf connected to this pin. sgnd (pin 4/pin 7): signal ground. all small-signal components and compensation components should con- nect to this ground, which in turn connects to pgnd at one point. margin1 (pin 5/pin 8): the msb logic input for the margining function. together with the margin0 pin determines whether the ic is in margin high, margin low, or no margin state. this pin has a 50k internal pull-down resistor. margin0 (pin 6/pin 9): the lsb logic input for the margining function. together with the margin1 pin determines whether the ic is in margin high, margin low, or no margin state. this pin has a 50k internal pull-down resistor. i on (pin 7/pin 10): on-time current input. tie a resistor from this pin to ground to set the one-shot timer current and thereby set the switching frequency. v refin (pin 8/pin 11): error amplifier reference input. the voltage at this pin must be greater than 0.5v and less than 1v. v refout (pin 9/pin 12): buffered internal 0.6v reference output. the maximum current sinking limit is 50 a at this pin. do not put a filter capacitor larger than 100pf on this pin. mpgm (pin 10/pin 13): programmable margining input. a resistor from this pin to ground sets the margining current. this current, together with the resistor between the v refout and v refin pins, determines the margining voltage offset. track/ss (pin 11/pin 14): output voltage tracking and soft start input. when the ic is configured to be the master of two outputs, a capacitor to ground at this pin sets the ramp rate for the output voltage. when the ic is configured (uh package/g package) ion current vs v in current limit foldback input voltage (v) 0 ion current ( a) 15 25 3770 g22 510 20 30 35 80 60 40 140 120 20 100 0 r on = 82k
8 LTC3770 3770f uu u pi fu ctio s (uh package/g package) to be the slave of two outputs, the v fb voltage of the master ic is reproduced by a resistor divider and applied to this pin. an internal 1.4 a soft start current is charging this pin during the soft-start phase. pllfltr (pin 12/pin 15): the phase-locked loop? lowpass filter is tied to this pin. the voltage at this pin defaults to 1.18v when the ic is not synchronized with an external clock at the pllin pin. pllin (pin 13/pin 16): external synchronization input to phase detector. this pin is internally terminated to sgnd with a 50k resistor. v in (pin 14/pin 17): main input supply. decouple this pin to pgnd with a capacitor (0.1 f to 1 f). v insns (pin 15) uh package: v in voltage sense input. normally this pin is tied to v in . however, in certain applications when the ic is powered from a separate supply, v insns is tied to the upper mosfet supply to sense the v in voltage. the pin is co-bonded with v in in the ssop package. zv in (pin 16/pin 18): post-package zener-trim voltage input. under normal conditions this pin should always be connected to intv cc . z1 (pin 17/pin 19): post-package zener-trim control. this pin is a multifunctional pin used in production for post-package trimming and tracking. ground this pin under normal soft-start operation. connecting this pin to intv cc will turn off the soft-start current during tracking. z2 (pin 18/pin 20): post-package zener-trim control. this pin is used in production for post-package trimming. ground this pin or tie to intv cc under normal operation. intv cc (pin 19/pin 21): internal 5v regulator output. the control circuits are powered from this voltage. decouple this pin to pgnd with a minimum of 10 f low esr tantalum or ceramic capacitor. drv cc (pin 20) uh package gate: driver voltage input. normally connected to the intv cc regulated output. do not exceed 7v at this pin. this pin is co-bonded to intv cc internally in the ssop package. bg (pin 21/pin 22): bottom gate driver output. this pin drives the gate of the bottom n-channel mosfet between ground and intv cc . pgnd (pin 22/pin 23): power ground. connect this pin closely to the source of the bottom n-channel mosfet, the (? terminal of c vcc and the (? terminal of c in . sense (pin 23) uh package: current sense comparator input. the (? input to the current comparator is used to accurately kelvin sense the bottom side of the sense resistor or mosfet. this pin is co-bonded with pgnd internally in the ssop package. sense + (pin 24) uh package: current sense comparator input. the (+) input to the current comparator is normally connected to the sw node unless using a sense resistor. this pin is co-bonded with sw internally in the ssop package. sw (pin 25/pin 24): switch node. the (? terminal of the boot-strap capacitor cb connects here. this pin swings from a diode voltage drop below ground up to v in . tg (pin 26/pin 25): top gate drive output. this pin drives the top n-channel mosfet with a voltage swing equal to intv cc , superimposed on the switch node voltage sw. boost (pin 27/pin 26): boosted floating driver supply. the (+) terminal of the boot-strap capacitor cb connects here. this pin swings from a diode voltage drop below intv cc up to v in + intv cc . z0 (pin 28/pin 27): dead time control input. applying a dc voltage will vary the dead time between tg-low and bg-high transition. do not force a voltage higher than 5v on this pin. fcb (pin 29/pin 28): forced continuous input. connect this pin to sgnd to force continuous synchronization operation at low load, to intv cc to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. run (pin 30/pin 1): run control input. a voltage above 1.5v turns on the ic. forcing this pin below 1.5v shuts down the device.
9 LTC3770 3770f 80% ?v refin 2.0v 0.5v v rng 1 + + + + + 7 31 i on 29 fcb 14 v in 1 a r on v von i ion t on = (10pf) r sq 20k i cmp i rev q6 3.3 a run switch logic and anti- shoot through bg on fcnt f 0.6v ov 1 240k q1 q2 1.5v i th r c c c1 ea ss q4 3 8 9 11 sgnd r2 r1 run pgnd 22 pgood 32 drv cc 20 intv cc intv cc 19 sw 25 tg c b v in c in boost 27 + + ov uv c vcc v out m2 m1 l1 c out d b i thb v out 0.6v 4.8v v on r sense (optional)* sense + sense 23 24 sense + sense bg m2 *connection w/o sense resistor sw pgnd (0.5~2) v refin r3 + foldback + 0.25v + + v refout 0.6v ref v in 10k 90k 10k + 5 margin1 10 mpgm 1.18v r4 track/ss 12k foldback disabled at start-up* run 30 margin0 6 v fb 4 2 pllin pllfltr pll-sync 13 12 + v insns 15 17 18 28 z0 z1 z2 16 z vin + + 5v reg 1.4 a c ss 21 26 r r r intv cc fu ctio al diagra uu w (uh package) v on (pin 31/pin 2): on-time voltage input. connecting this pin to the output voltage makes the on-time propor- tional to v out . the comparator input defaults to 0.6v when the pin is grounded and defaults to 4.8v when the pin is tied to intv cc . pgood (pin 32/pin 3): power good output. open drain logic output that is pulled to ground when the output voltage is not within 10% of the regulation point, after the internal 25 s power bad mask timer expires. exposed pad (pin 33) uh package: signal ground. must be soldered to the pcb ground for electrical contact and optimum thermal performance. uu u pi fu ctio s (uh package/g package)
10 LTC3770 3770f operatio u main control loop the LTC3770 is a current mode controller for dc/dc step-down converters. in normal operation, the top mosfet is turned on for a fixed interval determined by a one-shot timer ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current com- parator i cmp trips, restarting the one-shot timer and initi- ating the next cycle. inductor current is determined by sensing the voltage between the sense (pgnd on g package) and sense + (sw on g package) pins using a sense resistor or the bottom mosfet on-resistance . the voltage on the i th pin sets the comparator threshold corresponding to inductor valley current. the error ampli- fier ea adjusts this voltage by comparing the feedback signal v fb from a reference voltage set by the v refin pin. if the load current increases, it causes a drop in the feedback voltage relative to the reference. the i th voltage then rises until the average inductor current again matches the load current. at low load currents, the inductor current can drop to zero and become negative. this is detected by current reversal comparator i rev which then shuts off m2, resulting in discontinuous operation. both switches will remain off with the output capacitor supplying the load current until the i th voltage rises above the zero current level (0.75v) to initiate another cycle. discontinuous mode operation is disabled by comparator f when the fcb pin is brought below 0.6v, forcing continuous synchronous operation. the operating frequency is determined implicitly by the top mosfet on-time and the duty cycle required to maintain regulation. the one-shot timer generates an on- time that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor r on . for applications with stringent constant frequency re- quirements, the LTC3770 can be synchronized with an external clock. by programming the nominal frequency of the LTC3770 the same as the external clock frequency, the LTC3770 behaves as a constant frequency part against the load and supply variations. overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback voltage exits a 10% window around the regulation point after the internal 25 s power bad mask timer expires. furthermore, in an overvoltage condition, m1 is turned off and m2 is turned on immediately and held on until the overvoltage condition clears. foldback current limiting is provided if the output is shorted to ground. as v fb drops, the buffered current threshold voltage i thb is pulled down and clamped to 0.9v. this reduces the inductor valley current level to one tenth of its maximum value as v fb approaches 0v. foldback current limiting is disabled at start-up. pulling the run pin low forces the controller into its shutdown state, turning off both m1 and m2. forcing a voltage above 1.5v will turn on the device. intv cc power power for the top and bottom mosfet drivers and most of the internal controller circuitry is derived from the intv cc pin. the top mosfet driver is powered from a floating bootstrap capacitor c b . this capacitor is re- charged from intv cc through an external schottky diode d b when the top mosfet is turned off. if the input voltage is low and intv cc drops below 3.2v, undervoltage lockout circuitry prevents the power switches from turning on.
11 LTC3770 3770f the basic ltc 3770 application circuit is shown in figure 12. external component selection is primarily de- termined by the maximum load current and begins with the selection of the sense resistance and power mosfet switches. the ltc 3770 uses either a sense resistor or the on-resistance of the synchronous power mosfet for determining the inductor current. the desired amount of ripple current and operating frequency largely deter- mines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specification. maximum sense voltage and v rng pin inductor current is determined by measuring the voltage across a sense resistance that appears between the sense (pgnd on g package) and sense + (sw on g package) pins. the maximum sense voltage is set by the voltage applied to the v rng pin and is equal to approximately (0.133)v rng . the current mode control loop will not allow the inductor current valleys to exceed (0.133)v rng /r sense . in practice, one should allow some margin for variations in the LTC3770 and external component values and a good guide for selecting the sense resistance is: r v i sense rng out max = 10 () an external resistive divider from intv cc can be used to set the voltage of the v rng pin between 0.5v and 2v resulting in nominal sense voltages of 50mv to 200mv. additionally, the v rng pin can be tied to sgnd or intv cc in which case the nominal sense voltage defaults to 50mv or 200mv, respectively. the maximum allowed sense voltage is about 1.33 times this nominal value. connecting the sense + and sense pins the LTC3770 comes in uh and g packages. the uh package ic can be used with or without a sense resistor. when using a sense resistor, place it between the source of the bottom mosfet, m2, and pgnd. connect the sense + and sense pins to the top and bottom of the sense resistor. using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. alternatively, one can eliminate the sense resistor and use the bottom mosfet as the current sense element by simply connecting the sense + pin to the sw pin and sense pin to pgnd. this improves efficiency, but one must carefully choose the mosfet on-resistance as dis- cussed below. power mosfet selection the LTC3770 requires two external n-channel power mosfets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the breakdown voltage v (br)dss , threshold voltage v (gs)th , on-resistance r ds(on) , reverse transfer capacitance c rss and maximum current i ds(max) . the gate drive voltage is set by the 5v intv cc supply. consequently, logic-level threshold mosfets must be used in LTC3770 applications. if the input voltage is expected to drop below 5v, then sub-logic level threshold mosfets should be considered. when the bottom mosfet is used as the current sense element, particular attention must be paid to its on- resistance. mosfet on-resistance is typically specified with a maximum value r ds(on)(max) at 25 c. in this case, additional margin is required to accommodate the rise in mosfet on-resistance with temperature: r r ds on max sense t ()( ) = the t term is a normalization factor (unity at 25 c) accounting for the significant variation in on-resistance figure 1. r ds(on) vs temperature junction temperature ( c) ?0 t normalized on-resistance 1.0 1.5 150 3770 f01 0.5 0 0 50 100 2.0 applicatio s i for atio wu u u
12 LTC3770 3770f with temperature, typically about 0.4%/ c as shown in figure 1. for a maximum junction temperature of 100 c, using a value t = 1.3 is reasonable. the power dissipated by the top and bottom mosfets strongly depends upon their respective duty cycles and the load current. when the LTC3770 is operating in continuous mode, the duty cycles for the mosfets are: d v v d vv v top out in bot in out in = = the resulting power dissipation in the mosfets at maxi- mum output current are: p top = d top i out(max) 2 t(top) r ds(on)(max) + k v in 2 i out(max) c rss f p bot = d bot i out(max) 2 t(bot) r ds(on)(max) both mosfets have i 2 r losses and the top mosfet includes an additional term for transition losses, which are largest at high input voltages. the constant k = 1.7a ? can be used to estimate the amount of transition loss. the bottom mosfet losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. operating frequency the choice of operating frequency is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. the operating frequency of LTC3770 applications is deter- mined implicitly by the one-shot timer that controls the on-time t on of the top mosfet switch. the on-time is set by the current out of the i on pin and the voltage at the v on pin according to: t v i pf on von ion = () 10 tying a resistor r on to sgnd from the i on pin yields an on- time inversely proportional to 1/3 v in . the current out of the i on pin is: i v r ion in on = 3 for a step-down converter, this results in approximately constant frequency operation as the input supply varies: f v vrpf h out von on z = ?) [] 310 to hold frequency constant during output voltage changes, tie the v on pin to v out . the v on pin has internal clamps that limit its input to the one-shot timer. if the pin is tied below 0.6v, the input to the one-shot is clamped at 0.6v. similarly, if the pin is tied above 4.8v, the input is clamped at 4.8v. in high v out applications, tie v on to intv cc . figures 2a and 2b show how r on relates to switching frequency for several common output voltages. r on (k ? ) 100 100 switching frequency (khz) 1000 1000 3770 f02a v out = 3.3v v out = 1.5v v out = 2.5v r on (k ? ) 10 100 switching frequency (khz) 1000 100 1000 3770 f02b v out = 3.3v v out = 12v v out = 5v figure 2a. switching frequency vs r on (v on = 0v) figure 2b. switching frequency vs r on (v on = intv cc ) applicatio s i for atio wu u u
13 LTC3770 3770f when there is no r on resistor connected to the i on pin, the on-time t on is theoretically infinite, which in turn could damage the converter. to prevent this, the LTC3770 will detect this fault condition and provide a minimum i on current of 5 a to 10 a. changes in the load current magnitude will cause fre- quency shift. parasitic resistance in the mosfet switches and inductor reduce the effective voltage across the induc- tance, resulting in increased duty cycle as the load current increases. by lengthening the on-time slightly as current increases, constant frequency operation can be main- tained. this is accomplished with a resistive divider from the i th pin to the v on pin and v out . the values required will depend on the parasitic resistances in the specific applica- tion. a good starting point is to feed about 25% of the voltage change at the i th pin to the v on pin as shown in figure 3a. place capacitance on the v on pin to filter out the i th variations at the switching frequency. the resistor load on i th reduces the dc gain of the error amp and degrades load regulation, which can be avoided by using the pnp emitter follower of figure 3b. minimum off-time and dropout operation the minimum off-time t off(min) is the smallest amount of time that the LTC3770 is capable of turning on the bottom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 250ns. the minimum off-time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: vv tt t in min out on off min on () () = + a plot of maximum duty cycle vs frequency is shown in figure 4. c von 0.01 f r von2 100k r von1 30k c c v out r c (3a) (3b) v on i th LTC3770 c von 0.01 f r von2 10k q1 2n5087 r von1 3k 10k c c 3770 f03 v out intv cc r c v on i th LTC3770 figure 3. correcting frequency shift with load current changes 2.0 1.5 1.0 0.5 0 0 0.25 0.50 0.75 3770 f04 1.0 dropout region duty cycle (v out /v in ) switching frequency (mhz) figure 4. maximum switching frequency vs duty cycle inductor selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ? = ? ? ? ? ? ? ? ? ? ? ? ? ? i v fl v v l out out in 1 lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specified maximum, the inductance applicatio s i for atio wu u u
14 LTC3770 3770f should be chosen according to: l v fi v v out lmax out in max = ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () 1 once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molyper- malloy or kool m cores. a variety of inductors designed for high current, low voltage applications are available from manufacturers such as sumida, panasonic, coil- tronics, coilcraft and toko. schottky diode d1 selection the schottky diode d1 shown in figure 12 conducts during the dead time between the conduction of the power mosfet switches. it is intended to prevent the body diode of the bottom mosfet from turning on and storing charge during the dead time, which can cause a modest (about 1%) efficiency loss. the diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. in order for the diode to be effective, the inductance between it and the bottom mos- fet must be as small as possible, mandating that these components be placed adjacently. the diode can be omit- ted if the efficiency loss is tolerable. c in and c out selection the input capacitance c in is required to filter the square wave current at the drain of the top mosfet. use a low esr capacitor sized to handle the maximum rms current. ii v v v v rms out max out in in out ? () ? this formula has a maximum at v in = 2v out , where i rms = i out(max) / 2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple ? v out is approximately bounded by: ?? + ? ? ? ? ? ? v i esr fc out l out 1 8 since ? i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signifi- cant ringing. when used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. to dampen input voltage transients, add a small 5 f to 50 f aluminum electrolytic capacitor with an esr in the range of 0.5 ? to 2 ? . high performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recom- mended to reduce the effect of their lead inductance. top mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns kool m is a registered trademark of magnetics, inc. applicatio s i for atio wu u u
15 LTC3770 3770f on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications 0.1 f to 0.47 f, x5r or x7r dielectric capacitor is adequate. discontinuous mode operation and fcb pin the fcb pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin above its 0.6v threshold enables discontinuous operation where the bottom mosfet turns off when inductor current reverses. the load current at which current reverses and discontinuous operation begins de- pends on the amplitude of the inductor ripple current and will vary with changes in v in . tying the fcb pin below the 0.6v threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. to prevent forcing current back into the main power supply, potentially boosting the input supply to a dangerous voltage level, forced continuous mode of operation is disabled when the track/ss voltage is 20% below the reference voltage during soft-start or tracking up. forced continuous mode of operation is also disabled when the track/ss voltage is below 0.1v during tracking down operation. during these two periods, the pgood signal is forced low. in addition to providing a logic input to force continuous operation, the fcb pin provides a mean to maintain a flyback winding output when the primary is operating in discontinuous mode. the secondary output v out2 is nor- mally set as shown in figure 5 by the turns ratio n of the transformer. however, if the controller goes into discon- tinuous mode and halts switching due to a light primary load current, then v out2 will droop. an external resistor divider from v out2 to the fcb pin sets a minimum voltage v out2(min) below which continuous operation is forced until v out2 has risen above its minimum. vv r r out min 2 06 1 4 3 () . =+ ? ? ? ? ? ? fault conditions: current limit and foldback the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the LTC3770, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i v r i limit sns max ds on t l =+ ? () () 1 2 the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs with the largest v in at the highest ambi- ent temperature, conditions that cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed mosfet junction temperature and the resulting value of i limit which heats the mosfet switches. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on- resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same percentage below the typical value as the maxi- mum lies above it. consult the mosfet manufacturer for further guidelines. to further limit current in the event of a short circuit to ground, the LTC3770 includes foldback current limiting. if the output falls by more than 60%, then the maximum sense voltage is progressively lowered to about one tenth of its full value. figure 5. secondary output loop v in LTC3770 sgnd fcb tg sw r3 r4 3770 f05 t1 1:n bg pgnd + c out2 1 f v out1 v out2 v in + c in 1n4148 + c out applicatio s i for atio wu u u
16 LTC3770 3770f intv cc regulator an internal p-channel low dropout regulator produces the 5v supply that powers the drivers and internal circuitry within the LTC3770. the intv cc pin can supply up to 50ma rms and must be bypassed to ground with a minimum of 10 f low esr tantalum capacitor or other low esr capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate drivers. applications using large mosfets with a high input voltage and high frequency of operation may cause the LTC3770 to exceed its maximum junction temperature rating or rms current rating. most of the supply current drives the mosfet gates. in continuous mode operation, this current is i gatechg = f(q g(top) + q g(bot) ). the junction temperature can be estimated from the equations given in note 2 of the electrical characteristics. for example, the LTC3770eg is limited to less than 14ma from a 30v supply: t j = 70 c + (14ma)(30v)(130 c/w) = 125 c for applications where more current is needed than intv cc could supply, intv cc could be driven by an external supply with a voltage higher than 5.3v. however, the intv cc pin should not exceed its absolute maximum voltage of 7v. external gate drive buffers the LTC3770 drivers are adequate for driving up to about 50nc into mosfet switches with rms currents of 50ma. applications with larger mosfet switches or operating at frequencies requiring greater rms currents will benefit from using external gate drive buffers such as the ltc1693. alternately, the external buffer circuit shown in figure 6 can be used. figure 6. optional external gate driver q1 fmmt619 gate of m1 tg boost sw q2 fmmt720 q3 fmmt619 gate of m2 bg 3770 f06 intv cc pgnd q4 fmmt720 10 ? 10 ? soft-start and tracking the LTC3770 has the ability to either soft start by itself with a capacitor or track the output of another supply. when the device is configured to soft start by itself, a capacitor should be connected to the track/ss pin. the LTC3770 is put in a low quiescent current shutdown state (iq < 30 a) if the run pin voltage is below 1.5v. the track/ss pin is actively pulled to ground in this shutdown state. once the run pin voltage is above 1.5v, the LTC3770 is powered up. a soft-start current of 1.4 a then starts to charge the soft-start capacitor c ss . pin z1 must be grounded for soft-start operation. note that soft-start is achieved not by limiting the maximum output current of the controller but by controlling the ramp rate of the output voltage. current foldback is disabled during this soft-start phase. during the soft-start phase, the LTC3770 is ramp- ing the reference voltage until it is 20% below the voltage set by the v refin pin. the force continuous mode is also disabled and pgood signal is forced low during this phase. the total soft-start time can be calculated as: t softstart = 0.8 ?v refin ?c ss /1.4 a when the device is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the track/ss pin. pin z1 should be tied to intv cc to turn off the soft-start current in this mode. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply output voltage. output voltage tracking the LTC3770 allows the user to program how its output ramps up and down by means of the track/ss pin. through this pin, the output can be set up to either coincidentally or ratiometrically track with another supply? output, as shown in figure 7. in the following discussions, v out1 refers to the master LTC3770? output and v out2 refers to the slave LTC3770? output. to implement the coincident tracking in figure 7a, connect an additional resistive divider to v out1 and connect its midpoint to the track/ss pin of the slave ic. the ratio of this divider should be selected the same as that of the slave ic? feedback divider shown in figure 8. in this tracking applicatio s i for atio wu u u
17 LTC3770 3770f figure 7. two different modes of output voltage tracking time (7a) coincident tracking v out1 v out2 output voltage time 3770 f07 (7b) ratiometric tracking v out1 v out2 output voltage figure 8. setup for coincident and ratiometric tracking r3 r1 r4 r2 r3 v out2 r4 (8a) coincident tracking setup to v fb1 pin to track/ss2 pin to v fb2 pin v out1 r1 r2 r3 v out2 r4 3770 f08 (8b) ratiometric tracking setup to v fb1 pin to track/ss2 pin to v fb2 pin v out1 + ii d1 track/ss2 0.6v v fb2 d2 d3 3770 f09 ea2 figure 9. equivalent input circuit of error amplifier mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking, the ratio of the divider should be exactly the same as the master ic? feedback divider. note that the pin z1 of the slave ic should be tied to intv cc so that the internal soft-start current is disabled in both tracking modes or it will introduce a small error on the tracking voltage depending on the absolute values of the tracking resistive divider. by selecting different resistors, the LTC3770 can achieve different modes of tracking including the two in figure 7. so which mode should be programmed? while either mode in figure 7 satisfies most practical applications, there do exist some tradeoffs. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. this can be better understood with the help of figure 9. at the input stage of the slave ic? error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. the top two current sources are of the same amplitude. in the coincident mode, the track/ss voltage is substantially higher than 0.6v at steady state and effectively turns off d1. d2 and d3 will therefore conduct the same current and offer tight matching between v fb2 and the internal preci- sion 0.6v reference. in the ratiometric mode, however, track/ss equals 0.6v at steady state. d1 will divert part of the bias current to make v fb2 slightly lower than 0.6v. although this error is minimized by the exponential i-v characteristic of the diode, it does impose a finite amount of output voltage deviation. furthermore, when the master ic? output experiences dynamic excursion (under load transient, for example), the slave ic output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. applicatio s i for atio wu u u
18 LTC3770 3770f margining margining is a way to program the reference voltage to the error amplifier to a voltage different from the default 0.6v. margining is useful for customers who want to stress their systems by varying supply voltages during testing. the reference voltage to the error amplifier is set according to the following equation when the margining function is enabled: v refin = 0.6v (1.18v/r4) ?r3 referring to the functional diagram, 0.6v is the buffered system reference at the v refout pin. r3 and r4 are resistors used for programming the amount of margining. v refin should be a voltage between 0.5v and 1v. there are two logic control pins, margin1 and margin0, to determine whether the margining function is enabled, margin up(+) or margin down(?. table 1 summarizes the configurations: table 1: margining function margin1 margin0 mode low low no margining low high margin up high low margin down high high no margining the buffered reference at v refout has the ability to source a large amount of current. however, it can only sink a maximum of 50 a of current. to increase the sinking capability of this reference, connect a resistor to ground at this pin. one may also be tempted to connect a large capacitor to this pin to filter out the noise. however, it is recommended that no larger than 100pf of capacitance should be connected to this pin. phase-locked loop and frequency synchronization the LTC3770 has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. this allows the top mosfet turn-on to be locked to the rising edge of an external source. the frequency range of the voltage controlled oscillator is 30% around the center frequency f o . the center frequency is the operating frequency discussed in the previous section. the LTC3770 incorporates a pulse detection circuit that will detect a clock on the pllin pin. in turn, it will turn on the phase- locked loop function. the pulse width of the clock has to be greater than 400ns and the amplitude of the clock should be greater than 2v. during the start-up phase, phase-locked loop function is disabled. when LTC3770 is not in synchronization mode, pllfltr pin voltage is set to around 1.18v. frequency synchronization is accomplished by changing the internal on-time current according to the voltage on the pllfltr pin. the phase detector used is an edge sensitive digital type which provides zero degrees phase shift between the external and internal pulses. this type of phase detector will not lock up on input frequencies close to the harmon- ics of the vco center frequency. the pll hold-in range, ? f h , is equal to the capture range, ? f c: ? f h = ? f c = 0.3 f o the output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the pllfltr pin. a simplified block diagram is shown in figure 10. if the external frequency (f pllin ) is greater than the oscil- lator frequency f o , current is sourced continuously, pull- ing up the pllfltr pin. when the external frequency is less than f o , current is sunk continuously, pulling down the pllfltr pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. thus the voltage on the pllfltr pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable digital phase/ frequency detector pllin pllfltr 2.4v c lp 3770 f10 r lp vco figure 10. phase-locked loop block diagram applicatio s i for atio wu u u
19 LTC3770 3770f operating point the phase comparator output is open and the filter capacitor c lp holds the voltage. the LTC3770 pllin pin must be driven from a low impedance source such as a logic gate located close to the pin. the loop filter components (c lp , r lp ) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp =10k ? and c lp is 0.01 f to 0.1 f. dead time control to further optimize the efficiency, the LTC3770 gives users some control over the dead time of the top gate low and bottom gate high transition. by applying a dc voltage on the z0 pin, the tg low bg high dead time can be programmed. because the dead time is a strong function of the load current and the type of mosfet used, users need to be careful to optimize the dead time for their particular applications. figure 11 shows the relation be- tween the tg low bg high dead time by varying the z0 voltages. for an application using LTC3770 with load current of 5a and ir7811w mosfets, the dead time could be optimized. to make sure that there is no shoot-through under all conditions, a dead time of 70ns is selected. this corresponds to a dc voltage about 2.6v on z0 pin. this voltage can easily be generated with a resistor divider off intv cc . efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3770 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the efficiency to drop at high output currents. in continuous mode the average output current flows through l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 ? and r l = 0.005 ? , the loss will range from 15mw to 1.5w as the output current varies from 1a to 10a. 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is significant at input voltages above 20v and can be estimated from: transition loss ? (1.7a ? ) v in 2 i out c rss f 3. intv cc current. this is the sum of the mosfet driver and control currents. 4. c in loss. the input capacitor has the difficult job of filtering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. other losses, including c out esr loss, schottky diode d1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. z0 voltage (v) 0 tdead time (ns) 60 100 120 140 5 3770 f11 20 80 160 40 ?0 0 1 2 4 3 180 i out = 5a irt811w fets figure 11. tg low bg high dead time vs z0 voltage applicatio s i for atio wu u u
20 LTC3770 3770f if you make a change and the input current decreases, then the efficiency has increased. if there is no change in input current, then there is no change in efficiency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ? i load (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability prob- lem. the i th pin external components shown in figure 12 will provide adequate compensation for most applica- tions. for a detailed explanation of switching control loop theory see application note 76. design example as a design example, take a supply with the following specifications: v in = 5v to 28v (15v nominal), v out = 2.5v 5%, i out(max) = 10a, f = 450khz. first, calculate the timing resistor with v on = v out : r v v khz pf k on = ()( )() = ? 25 3 2 5 450 10 74 . . and choose the inductor for about 40% ripple current at the maximum v in : l v khz a v v h = ()()() ? ? ? ? ? ? ? = 25 450 0 4 10 1 25 28 13 . . . . selecting a standard value of 1.8 h results in a maximum ripple current of: ? = () () ? ? ? ? ? ? = i v khz h v v a l 25 450 1 8 1 25 28 28 . . . . next, choose the synchronous mosfet switch. choosing a si4874 (r ds(on) = 0.0083 ? (nom) 0.010 ? (max), ja = 40 c/w) yields a nominal sense voltage of: v sns(nom) = (10a)(1.3)(0.0083 ? ) = 108mv tying v rng to 1.1v will set the current sense voltage range for a nominal value of 110mv with current limit occurring at 146mv. to check if the current limit is acceptable, assume a junction temperature of about 80 c above a 70 c ambient with 150 c = 1.5: i mv aa limit () ? () + () = 146 15 0010 1 2 28 11 .. . and double check the assumed t j in the mosfet: p vv v aw bot = ()() ? () = 28 2 5 28 11 15 0010 165 2 ? .. . t j = 70 c + (1.65w)(40 c/w) = 136 c because the top mosfet is on for such a short time, an si4884 r ds(on)(max) = 0.0165 ? , c rss = 100pf, ja = 40 c/w will be sufficient. checking its power dissipation at current limit with 100 c = 1.4: p v v a v a pf khz www top = ()() ? () + ()( )( )( )( ) =+= 25 28 11 1 4 0 0165 1 7 28 11 100 250 025 037 062 2 2 . .. . .. . t j = 70 c + (0.62w)(40 c/w) = 95 c the junction temperature will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking on the board will be necessary in this circuit. c in is chosen for an rms current rating of about 3a at 85 c. the output capacitors are chosen for a low esr of 0.013 ? to minimize output voltage changes due to induc- tor ripple current and load steps. the ripple voltage will be only: ? v out(ripple) = ? i l(max) (esr) = (2.8a) (0.013 ? ) = 36mv however, a 0a to 10a load step will cause an output change of up to: ? v out(step) = ? i load (esr) = (10a) (0.013 ? ) = 130mv an optional 22 f ceramic output capacitor is included to minimize the effect of esl in the output ripple. the complete circuit is shown in figure 12. applicatio s i for atio wu u u
21 LTC3770 3770f to set a 25% margining, select the resistors r3, r4 such that v refin = 0.6 25% ?0.6 or 118 3 4 25 0 6 . % . r r = r4 8r3 choose r3 to be 10k, r4 to be 82k for this application. pc board layout checklist when laying out a pc board follow one of two suggested approaches. the simple pc board layout requires a dedi- cated ground plane layer. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. place c in , c out , mosfets, d1 and inductor all in one compact area. it may help to have some components on the bottom side of the board. use an immediate via to connect the components to ground plane including sgnd and pgnd of LTC3770. use several bigger vias for power components. use compact plane for switch node (sw) to improve cooling of the mosfets and to keep emi down. use planes for v in and v out to maintain good voltage filtering and to keep power losses low. flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power component. you can connect the copper areas to any dc net (v in , v out , gnd or to any other dc rail in your system). figure 12. design example: 2.5v/10a at 450khz 3770 f12 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 run v on pgood v rng v fb i th sgnd margin1 margin0 i on v refin v refout mpgm track/ss run fcb z0 boost tg sw pgnd bg intv cc z1 z2 z vin v in pllin pllfltr intv cc 5v LTC3770eg l1: sumida cep125-1r8mc-h c out : cornell dubilier esre181e04b c in : united chemicon thcr60e1h106zt r6 11k r5 39k r c 20k r3 10k r2 95.3k r on 75k r4 82k r pg 100k cc1 500pf cc2 100pf c ss 0.1 f cv cc 10 f cv in 0.1 f db cmdsh-3 d1 b340a + c out3 23 f x5r x2 c out1-2 180 f 4v x2 v out 2.5v 10a v in 5v to 28v + c in 10 f 50v x3 cb 0.22 f m1 si4884 l1 1.8 h m2 si4874 + r1 30.1k r8 51k r7 47k applicatio s i for atio wu u u
22 LTC3770 3770f u package descriptio g package 28-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) g28 ssop 0204 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 14 13 9.90 ?10.50* (.390 ?.413) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12 when laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper opera- tion of the controller. segregate the signal and power grounds. all small signal components should return to the sgnd pin at one point which is then tied to the pgnd pin close to the source of m2. place m2 as close to the controller as possible, keeping the pgnd, bg and sw traces short. connect the input capacitor(s) c in close to the power mosfets. this capacitor carries the mosfet ac current. keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. connect the intv cc decoupling capacitor c vcc closely to the intv cc and pgnd pins. connect the top driver boost capacitor c b closely to the boost and sw pins. connect the v in pin decoupling capacitor c f closely to the v in and pgnd pins. applicatio s i for atio wu u u
23 LTC3770 3770f u package descriptio uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u typical applicatio 1.8v/5a at 450khz with tracking intv cc 24 23 22 21 20 19 18 17 91011 1213141516 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 pllfltr pllin v in v insns zv in LTC3770euh 3770 ta02a pgood v on run fcb fcb v refout mpgm track/ss z0 boost tg sw sense+ sense pgnd bg drv cc intv cc z2 z1 v rng v fb i th sgnd r1 30.1k r2 60.4k cc1 1000pf margin1 v refin i on margin0 l1: bi tech 1.8 h hm65-h1r8-tb m1, m2: philips ph3230 c in : tdk c4532x5r1h685m c out : panasonic eefue0g181r margin1 run track/ss pgood margin0 r on 75k r5 10k r c 10k r6 200k r run 51k r pg 100k cc2 100pf c f 220pf v cc 5v m1 ph3230 cv cc 10 f db cmdsh-3 d1 b340a c in 6.8 f 50v x3 v out 1.8v 5a v in 4v to 28v cb 0.22 f m2 ph3230 + l1 1.8 h c out3 22 f x5r x2 c out 180 f 4v x2 + r8 51k r7 47k 1000pf 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 0.23 typ (4 sides) 31 1 2 32 bottom view?xposed pad 3.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0603 0.50 bsc 0.200 ref 0.00 ?0.05 0.70 0.05 3.45 0.05 (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout
24 LTC3770 3770f part number description comments ltc1622 550khz step-down controller 8-pin msop; synchronizable; soft-start; current mode ltc1625/ltc1775 no r sense current mode synchronous step-down controller 97% efficiency; no sense resistor; 16-pin ssop ltc1628/ltc3728 dual, 2-phase synchronous step-down controller power good output; minimum input/output capacitors; 3.5v v in 36v ltc1735 high efficiency, synchronous step-down controller burst mode operation; 16-pin narrow ssop; 3.5v v in 36v ltc1736 high efficiency, synchronous step-down controller with 5-bit vid mobile vid; 0.925v v out 2v; 3.5v v in 36v ltc1772 sot-23 step-down controller current mode; 550khz; very small solution size ltc1773 synchronous step-down controller up to 95% efficiency, 550khz, 2.65v v in 8.5v, 0.8v v out v in , synchronizable to 750khz ltc1778 wide range, no r sense synchronous step-down controller gn16-pin, 0.8v fb reference ltc1876 2-phase, dual synchronous step-down controller with 3.5v v in 36v, power good output, 300khz operation step-up regulator ltc3708 dual, 2-phase, no r sense synchronous step-down controller with fast transient response reduces c out ; 4v v in 36v, output tracking 0.6v v out 6v; 2-phase operation reduces c in ltc3713 low v in high current synchronous step-down controller 1.5v v in 36v, 0.8v v out (0.9)v in , i out up to 20a ltc3731 3-phase synchronous step-down controller 600khz; up to 60a output ltc3778 low v out , no r sense synchronous step-down controller 0.6v v out (0.9)v in , 4v v in 36v, i out up to 20a burst mode is a registered trademark of linear technology corporation. ? linear technology corporation 2004 lt/tp 1104 1k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts u typical applicatio typical application 2.5v/10a synchronized at 450khz r8 51k r7 47k intv cc 24 23 22 21 20 19 18 17 91011 1213141516 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 pllfltr pllin pllin v in v insns zv in LTC3770euh 3770 ta02b pgood v on run fcb fcb v refout mpgm track/ss z0 boost tg sw sense+ sense pgnd bg drv cc intv cc z2 z1 v rng v fb i th sgnd r1 30.1k r2 95.3k cc1 1000pf margin1 v refin i on margin0 margin1 run pgood margin0 r on 75k r5 10k r c 10k r6 82k r pl 10k rv in 10 ? r run 51k r4 39k r3 11k r pg 100k cc2 100pf c f 220pf cv in 0.01 f 0.1 f c ss 0.1 f m1 ph3230 cv cc 10 f db cmdsh-3 d1 b340a c in 10 f 50v x3 v out 2.5v 10a v in 5v to 28v cb 0.22 f m2 ph3230 l1 1.8 h c out3 22 f x5r x2 c out 180 f 4v x2 + c p 1000pf c pl 0.01 f l1: bi tech 1.8 h hm65-h1r8-tb m1, m2: philips ph3230 c in : tdk c4532x5r1h685m c out : panasonic eefue0g181r 1000pf

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